The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to nFET and pFET devices formed on strain relaxed buffers and the fabrication of such devices.
Various semiconductor devices benefit from the use of strain-relaxed buffer layers such as those comprising fully relaxed silicon germanium (SiGe). Strain-relaxed buffers (SRBs) can act as virtual substrates on which to grow semiconductor layers having lattice constants different from those of the original substrates, for example silicon (001). The SRBs can support strained or relaxed layers. The SRBs should be relaxed to help avoid the generation of crystal imperfections such as threading dislocations in the layer(s) grown thereon. Such defects are known to have deleterious effects on the properties of electronic and optoelectronic devices. The crystalline quality of a relaxed SiGe layer can be improved by, for example, growing compositionally graded buffer layers (GBL) with a thickness of up to several micrometers. Graded buffer layers are grown with increasing germanium concentration as the thickness increases. Molecular beam epitaxy (MBE) is one suitable technique for growing graded SiGe buffer layers. Other techniques are known to the art. As the surface roughness of buffer layers obtained using such a technique may not be optimal, chemical mechanical polishing (CMP) may be necessary. Another technique used for fabricating a relaxed Si1−xGex buffer having reduced levels of threading dislocations includes epitaxially depositing a pseudomorphic or nearly pseudomorphic Si1−xGex layer on the surface of a silicon substrate, ion implanting atoms of a light element into the substrate, and annealing the substrate at a temperature above 650° C. Reduction of threading dislocations (TD) density is obtained by plastic relaxation, which by definition works based on dislocation generation to relax the lattice mismatched crystals.
Exemplary devices that may be formed using strain-relaxed silicon germanium layers include fin-type field-effect transistors (FinFETs), metal oxide field effect transistors (MOSFETs), and strained silicon-based complementary metal oxide semiconductor (CMOS) devices. Some nFET devices require silicon layers under tensile strain to enhance electron mobility. Other devices or elements such as pFET devices require semiconductor layers under compressive strain. The amount of strain on a silicon or silicon germanium layer grown epitaxially on a relaxed Si1−xGex layer can be engineered by providing an atomic percentage of germanium within a selected range. A current technique involves the use of SiGe alloys having, for example, twenty-five percent (25%) germanium in the buffer layer (Si0.75Ge0.25) and fifty percent germanium (Si0.5Ge0.5) in the adjoining pFET layer. Gate stack fabrication on SiGe alloys containing twenty-five percent (25%) germanium is well understood, but formation of a reliable gate stack on SiGe alloys having higher germanium contents can be challenging. Strain relaxed buffer layers allow dual channel materials to be provided on the same substrate employed to fabricate integrated circuits including, for example, FinFET devices.
FIGS. 1-4 schematically illustrate an exemplary sequence of steps for forming a finned structure useful for forming FinFET devices on a bulk silicon substrate. FIG. 1 shows a structure 20 including a bulk silicon substrate 22 and a strain relaxed buffer (SRB) layer 24 on the substrate. The SRB layer is a silicon germanium layer, for example (Si0.75Ge0.25). The SRB layer is subjected to ion implantation to form a p-well region 26 in the nFET region of the structure and an n-well region 28 in the pFET region of the structure 20. Boron ions 27 are implanted to form the p-well region 26 while the pFET region is masked. Arsenic ions 29 are used to form the n-well region 28 while the nFET region is masked. As known in the art, punch through stop (PTS) implantation reduces the punch through current in FinFET devices formed using bulk silicon substrates. As shown in FIG. 2, a silicon layer 30 is grown epitaxially on the p-well in the nFET region of the structure while the pFET region is masked and a silicon germanium layer 31 is grown on the n-well region 28 while the nFET region is masked. The silicon germanium layer may have the composition Si0.60Ge0.40 and will accordingly be under compressive strain when grown on an SRB layer having a lower percentage of germanium. The silicon layer 30 is under tensile strain. Fins 32, 33 are formed from the silicon and silicon germanium layers 30, 31, respectively. Fins having relatively small widths, for example six to ten nanometers (6-10 nm), can be formed using sidewall image transfer (SIT) processes. Photolithographic processes can be employed for forming fins having relatively large widths. Portions of the p-well and n-well may be removed during fin formation, as schematically illustrated, leaving PTS regions at the bottom portions of the fins. While shown as having vertical side walls, the fins may instead have generally triangular configurations with wider bases than top portions. The spaces between fins are partially filled with a dielectric material such as silicon dioxide. The deposited dielectric material is etched back to form a dielectric layer 34 of desired thickness. The heights of the fins are determined by the thickness of the dielectric layer 34, as schematically illustrated in FIG. 4.
Conventional process flows relating to the fabrication of finned semiconductor devices includes steps such as ion implantation and annealing. Problems may arise from damage caused by ion implantation in the SiGe SRB, leading to defect nucleation and defect movement. Such defects 35 are schematically illustrated in FIG. 4. (The silicon substrate beneath the SRB layer is not shown in FIGS. 2-4 to simplify the drawings.) Enhanced diffusion of n-doped species used to form the PTS region in the pFET region of the structure increases the difficulty in forming gate stacks on the silicon germanium fins 33. Arsenic has a much higher diffusion rate in silicon germanium than in silicon, leading to unwanted diffusion into the channel regions of the silicon germanium fins 33. Such diffusion is schematically illustrated in FIG. 4. Phosphorus, while having a slower diffusion rate than arsenic, likewise tends to diffuse upward from the PTS region into the channel regions of the silicon germanium fins 33 and laterally into the adjoining p-well region. The formation of reliable gate stacks in the pFET region is more challenging when the fins 33 have been subjected to arsenic or phosphorus diffusion.
Fin-type field-effect transistors (FinFETs) as discussed above have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator substrates or bulk semiconductor substrates. In bulk FinFETs, active fin heights are set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures involve the fabrication of a dummy gate followed by fabrication of other transistor elements and replacement of the dummy gate with actual gate materials.